Many semiconductor devices employ MOS transistors as switching devices. As semiconductor devices become more highly integrated, the MOS transistors have, typically, been scaled down. The electrical characteristics of the MOS transistors may directly influence performance of the semiconductor devices.
Recently, double gate MOS transistors have been introduced to improve the electrical characteristics of MOS transistors that are suitable for the highly-integrated semiconductor device. A double gate MOS transistor, typically, includes a source region and a drain region respectively formed at both sides of a channel region. A top gate electrode and a bottom gate electrode are disposed on and under the channel region. In addition, the top gate electrode is electrically connected to the bottom gate electrode. Therefore, if a gate voltage higher than the threshold voltage is applied to the gate electrodes, inversion layers are formed at a top surface and a bottom surface of the channel region. As a result, the double gate MOS transistor exhibits a large on-current even in a limited area as compared to a conventional MOS transistor having a single gate electrode. Accordingly, a semiconductor device employing double gate MOS transistors may provide a higher operating speed than devices without such transistors.
Double gate MOS transistors are described, for example, in U.S. Pat. No. 6,004,837 to Gambino, et al., entitled “dual-gate SOI transistor”. According to U.S. Pat. No. 6,004,837, a MOS transistor is provided having a top gate electrode and a bottom gate electrode, formed on a silicon on insulator (SOI) substrate.